Alright, so I'll prefix this with saying I am working on my Senior Project for my Computer Systems Engineering degree.
My project includes a touch screen interface with a small amount of graphics. Implementing this in pure hardware would be a state machine nightmare so I have chosen to include a soft-core processor in my design. I am using the DE0 development board which includes an Altera Cyclone III FPGA. I'm sure there are fine Xilinx boards out there but I am tired of the ISE not supporting SystemVerilog and having to generate an EDIF in Precision only to watch the ISE puke its guts on the floor during programming. This also means I don't have to pull a Precision licence out of my arse. For similar reasons, I wanted to avoid the NIOS processor core so I wouldn't have to deal with licencing. Sure, Altera is really nice to students and would undoubtedly provide me with a 1 year licence if I asked nicely but that is beside the point.
So I created an account on open cores and acquired the processor code via svn at http://opencores.org/openrisc,or1200
I was lazy so I threw all of the files into Quartus and recompiled. Nothing was totally broken so I took a moment to put my feet up and contemplate which file had the module I should instantiate. Overwelmed, I returned to the site and began reading the tutorial at http://emsys.denayer.wenk.be/?project=empro&page=cases&id=6
I found the top module and instantiated that without connecting anything. Compiling revealed that it appears to compile despite having it all optimized out. I still don't know what to do about the wishbone buses and decided to download the vmware image (which I have yet to try). The link on the site is broken but the file can be found at http://opencores.org/ocsvn/or1k/web_uploads/vmware_image/
I'll post here as I figure out more.
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