OR1200 processing instructions

Well, after a tiny amount of sweat and tears I got the OR1200 hooked to a ROM for instructions and was able to execute them. The instructions I am currently running are from the example in the VMWare image. Before I actually sit down and write any C code myself I am investigating linker scripts and how to do what I want.

Unfortunately Quartus does not support parameterized filenames in the Verilog $readmemh command. This means that the filename must be hard coded and the module is single purpose. Bummer. I submitted a feature request to Altera but my hopes aren't high.

Here is the code from what I did:

http://pastebin.com/27b7WXFq

http://pastebin.com/LbUQjDRF

http://pastebin.com/mW3mdfMH

http://pastebin.com/SbTTFJUB

It is worth noting that I did not hook anything to the data Wishbone Bus. Instead I asserted retry so it will infinity loop trying to perform a bus transaction. Eventually I will insert a traffic cop and combine the buses.

Quartus Programmer [Linux]

In other news, my laptop is running fedora instead of Windows 7 like my desktop. I haven't used my laptop to program my board before so I gave it a go. Turns out its a pain. There is a permission problem, so you need to create a udev rule. After a bunch of research and partial solutions to the dreaded "Unable to lock chain (Insufficient port permissions)" problem I crafted the following udev rule which seems to work nicely. This issue is udev changes the permissions in /dev but quartus uses /proc so we need an extra command to update that as well.

BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6001", SYMLINK+="usbblaster", MODE="0666", RUN+="/bin/chmod 0666 /proc/bus/usb/$env{BUSNUM}/$env{DEVNUM}"

OR1200 Continued

Working on making progress on the processor. Thus far I have http://pastebin.com/qSLuvy3X

It uses the RAM_wb IP for the instruction RAM (With a few bug fixes). This doesn't really provide a way to load a boot rom as far as I can tell but I will worry about that later when *something* works. I've also been fiddling with the VMWare image which involved replacing hard coded IP addresses with opencores.org in three scripts. I'll see later if I can at least update two of them myself. The first is unfortunately embedded in the VMWare image, I may still be able to update it and see about making it also work with VirtualBox.

I am surprised that anyone has ever used this stuff and gotten it to work. No wonder companies are willing to fork out so much money for a solution.

OR1200: My first impressions of OpenRISC

Alright, so I'll prefix this with saying I am working on my Senior Project for my Computer Systems Engineering degree.

My project includes a touch screen interface with a small amount of graphics. Implementing this in pure hardware would be a state machine nightmare so I have chosen to include a soft-core processor in my design. I am using the DE0 development board which includes an Altera Cyclone III FPGA. I'm sure there are fine Xilinx boards out there but I am tired of the ISE not supporting SystemVerilog and having to generate an EDIF in Precision only to watch the ISE puke its guts on the floor during programming. This also means I don't have to pull a Precision licence out of my arse. For similar reasons, I wanted to avoid the NIOS processor core so I wouldn't have to deal with licencing. Sure, Altera is really nice to students and would undoubtedly provide me with a 1 year licence if I asked nicely but that is beside the point.

So I created an account on open cores and acquired the processor code via svn at http://opencores.org/openrisc,or1200

I was lazy so I threw all of the files into Quartus and recompiled. Nothing was totally broken so I took a moment to put my feet up and contemplate which file had the module I should instantiate. Overwelmed, I returned to the site and began reading the tutorial at http://emsys.denayer.wenk.be/?project=empro&page=cases&id=6

I found the top module and instantiated that without connecting anything. Compiling revealed that it appears to compile despite having it all optimized out. I still don't know what to do about the wishbone buses and decided to download the vmware image (which I have yet to try). The link on the site is broken but the file can be found at http://opencores.org/ocsvn/or1k/web_uploads/vmware_image/

I'll post here as I figure out more.